1. Field
The embodiment relates to a DC-DC conversion circuit, a DC-DC conversion control circuit, and a DC-DC conversion control method.
2. Description of the Related Art
In a portable electronics device such as a notebook personal computer, a secondary battery is used as a power supply. In general, a voltage supplied by the secondary battery decreases as a discharge of the secondary battery advances, and therefore, a power supply circuit using a DC-DC converter (DC-DC conversion circuit) is mounted so as to keep the voltage used inside the portable electronics device constant. Besides, in the portable electronics device, a charging circuit using the DC-DC converter is also mounted so that the secondary battery can be charged easily by connecting an external power supply via an AC adapter and so on. It is general that the portable electronics device is driven by using a power supply of the secondary battery when the external power supply is not connected, and driven by using the power supply of the external power supply when the external power supply is connected.
In the DC-DC converter, it is very important to prevent an inrush current at a start time of the DC-DC converter. For example, in a DC-DC converter in a PWM control method, a method is known in which the inrush current is prevented by forcibly reducing a pulse width of a control signal turning on/off a switching element by using a dead time control circuit, and then increasing the pulse width gradually in accordance with a passage of time at the start time of the DC-DC converter. In addition to the above, a method is also known in which the inrush current is prevented by an output slope control increasing an output voltage of the DC-DC converter gradually from “0” (zero) V at the start time of the DC-DC converter.
FIG. 1 shows an example of a DC-DC converter. A DC-DC converter CNV is configured as a constant-voltage control type DC-DC converter, and has a main switching transistor T1, a synchronous rectification transistor T2, a choke coil L1, a smoothing capacitor C1, a soft-start capacitor CS1, and a control circuit CTL. The main switching transistor T1 is configured by an n-type transistor. An input pin of the main switching transistor T1 is connected to an input pin P1 receiving an input voltage V1. An output pin of the main switching transistor T1 is connected to one end of the choke coil L1. A control pin of the main switching transistor T1 receives an output signal QP of a PWM comparator PCMP in the control circuit CTL.
The synchronous rectification transistor T2 is configured by an n-type transistor. An input pin of the synchronous rectification transistor T2 is connected to a ground line. An output pin of the synchronous rectification transistor T2 is connected to one end of the choke coil L1. A control pin of the synchronous rectification transistor T2 receives an output signal /QP of the PWM comparator PCMP in the control circuit CTL. The other end of the choke coil L1 is connected to an output pin P2 supplying an output voltage Vo. The smoothing capacitor C1 is provided to smooth the output voltage Vo, and connected between the output pin P2 and the ground line. One end of the soft-start capacitor CS1 is connected to a second non-inverting input pin between a first and second non-inverting input pins of an error amplifier ERA1 in the control circuit CTL. The other end of the soft-start capacitor CS1 is connected to a ground line.
The control circuit CTL is configured by including a constant-current circuit I1, switch circuits SW1A, SW1B, a discharging resistor RD1, resistors R1, R2, a voltage generator E1, the error amplifier ERA1, a triangular wave oscillator OSC, and the PWM comparator PCMP. The constant-current circuit I1 and the switch circuit SW1A are connected in series between a supply line of a power supply voltage Vh and one end of the soft-start capacitor CS1 (the second non-inverting input pin of the error amplifier ERA1). The switch circuit SW1B and the discharge resistor RD1 are connected in series between one end of the soft-start capacitor CS1 (the second non-inverting input pin of the error amplifier ERA1) and the ground line. The switch circuit SW1A turns on-state in response to a start request of the DC-DC converter CNV, and turns off-state in response to a stop request of the DC-DC converter CNV. The switch circuit SW1B turns on-state in response to the stop request of the DC-DC converter CNV, and turns off-state in response to the start request of the DC-DC converter CNV. The resistors R1, R2 are connected in series between the output pin P2 and the ground line. The voltage generator E1 generates a reference voltage Ve1.
The error amplifier ERA1 amplifies a voltage difference between a lower voltage between the voltage of the first non-inverting input pin and the voltage of the second non-inverting input pin, and a voltage of an inverting input pin, to generate an output signal DF1. The error amplifier ERA1 receives the reference voltage Ve1 at the first non-inverting input pin, receives a voltage Vs1 (a voltage of a connection node of the switch circuits SW1A, SW1B) generated by the soft-start capacitor CS1 at the second non-inverting input pin, and receives a voltage Vd (a voltage of a connection node of the resistors R1, R2) dividing the output voltage Vo by the resistors R1, R2 at the inverting input pin. Accordingly, the error amplifier ERA1 generates the output signal DF1 by amplifying the voltage difference between the voltage Vs1 and the voltage Vd when the voltage Vs1 is lower than the reference voltage Ve1, and generates the output signal DF1 by amplifying the voltage difference between the reference voltage Ve1 and the voltage Vd when the voltage Vs1 is higher than the reference voltage Ve1. The triangular wave oscillator OSC generates a triangular wave signal TW having a predetermined cycle. For example, a minimum value of a voltage of the triangular wave signal TW is 1.0 V, and a maximum value of the voltage of the triangular wave signal TW is 2.0 V.
The PWM comparator PCMP is a voltage-pulse width converter comparing the voltage of a non-inverting input pin and the voltage of an inverting input pin, setting the output signal QP (/QP) at a high level (low level) when the voltage of the inverting input pin is lower, and setting the output signal QP (/QP) at a low level (high level) when the voltage of the inverting input pin is higher. The PWM comparator PCMP receives the output signal DF1 of the error amplifier ERA1 at the non-inverting input pin, and receives the triangular wave signal TW at the inverting input pin. Accordingly, the PWM comparator PCMP sets the output signal QP at the high level when the voltage of the output signal DF1 of the error amplifier ERA1 is higher than the voltage of the triangular wave signal TW, and sets the output signal QP at the low level when the voltage of the output signal DF1 of the error amplifier ERA1 is lower than the voltage of the triangular wave signal TW.
In the DC-DC converter CNV having the constitution as stated above, when the main switching transistor T1 turns on-state, the synchronous rectification transistor T2 turns off-state, and a current is supplied to a load from an input side via the choice coil L1. A voltage difference between an input voltage Vi and the output voltage Vo is applied to both ends of the choke coil L1, and therefore, the current flowing in the choke coil L1 increases in accordance with the passage of time and the current supplied to the load also increases in accordance with the passage of time. Besides, the current flows in the choke coil L1, and thereby, energy is accumulated at the choke coil L1. When the main switching transistor T1 turns off-state, the synchronous rectification transistor T2 turns on-state, and the energy accumulated at the choke coil L1 is discharged. At this time, the output voltage Vo is represented by an expression (1) using an on-term Ton of the main switching transistor T1, an off-term Toff of the main switching transistor T1, and the input voltage Vi.Vo={Ton/(Ton+Toff)}×Vi  (1)
Besides, the current flowing in the choke coil L1 flows from the input side to the output side during the on-term of the main switching transistor T1, and it is supplied via the synchronous rectification transistor T2 during the off-term of the main switching transistor T1. Accordingly, an average input current Ii is represented by an expression (2) using the on-term Ton of the main switching transistor T1, the off-term Toff of the main switching transistor T1, and an output current Io.Ii={Ton/(Ton+Toff)}×Io  (2)
Consequently, when the output voltage Vo varies resulting from a variation of the input voltage Vi, it is possible to keep the output voltage Vo constant by detecting the variation of the output voltage Vo, and controlling a ratio of the on-term/off-term of the main switching transistor T1. Similarly, when the output voltage Vo varies resulting from a variation of the load, it is possible to keep the output voltage Vo constant by detecting the variation of the output voltage Vo, and controlling the ratio of the on-term/off-term of the main switching transistor T1.
FIG. 2 shows operations of the PWM comparator in FIG. 1. The PWM comparator PCMP sets the output signal QP at the high level when the voltage of the output signal DF1 of the error amplifier ERA1 is higher than the voltage of the triangular wave signal TW, and sets the output signal QP at the low level when the voltage of the output signal DF1 of the error amplifier ERA1 is lower than the voltage of the triangular wave signal TW. Accordingly, when the voltage of the output signal DF1 of the error amplifier ERA1 becomes low, the pulse width (high-level period) of the output signal QP of the PWM comparator PCMP becomes small, and when the voltage of the output signal DF1 of the error amplifier ERA1 becomes high, the pulse width of the output signal QP of the PWM comparator PCMP becomes large. As stated above, the PWM comparator PCMP generates the output signal QP with the pulse width in proportion to the voltage of the output signal DF1 of the error amplifier ERA1.
Consequently, during the period when the voltage Vs1 generated by the soft-start capacitor CS1 is higher than the reference voltage Ve1, the voltage difference between the reference voltage Ve1 and the voltage Vd (the voltage dividing the output voltage Vo by the resistors R1, R2) becomes large and the voltage of the output signal DF1 of the error amplifier ERA1 becomes high, when the output voltage Vo becomes low. As a result, the pulse width of the output signal QP of the PWM comparator PCMP becomes large, and the on-term of the main switching transistor T1 becomes long. On the other hand, when the output voltage Vo becomes high, the voltage difference between the reference voltage Ve1 and the voltage Vd becomes small, and the voltage of the output signal DF1 of the error amplifier ERA1 becomes low. As a result, the pulse width of the output signal QP of the PWM comparator PCMP becomes small, and the on-term of the main switching transistor T1 becomes short. As stated above, in the DC-DC converter CNV in the PWM control method, it is possible to control the output voltage Vo by controlling the ratio of the on-term/off-term of the main switching transistor T1.
Incidentally, the output voltage Vo is “0” (zero) V at a start time of the DC-DC converter CNV, and therefore, the voltage difference between the input voltage Vi and the output voltage Vo becomes maximum, and the voltage of the output signal DF1 of the error amplifier ERA1 also becomes maximum when it is assumed that the voltage of the first non-inverting input pin is lower than the voltage of the second non-inverting input pin at the error amplifier ERA1. In this case, the pulse width of the output signal QP of the PWM comparator PCMP becomes maximum, and the on-term of the main switching transistor T1 becomes maximum. Besides, a maximum current Ipeak flowing in the choke coil L1 is represented by an expression (3) using the input voltage Vi, the output voltage Vo, an inductance L of the choke coil L1, and the on-term Ton of the main switching transistor T1.Ipeak={(Vi−Vo)/L}×Ton  (3)
The output voltage Vo is “0” (zero) V at the start time of the DC-DC converter CNV, and therefore, the voltage applied to the choke coil L1 becomes maximum, and the on-term of the main switching transistor T1 becomes maximum. As a result, it can be seen that excessive inrush currents are generated at the choke coil L1 and the main switching transistor T1. The excessive inrush current is generated because the DC-DC converter CNV tries to increase the output voltage Vo from “0” (zero) V to a rated value (for example, 3.3 V) at one stroke.
However, at the start time of the DC-DC converter CNV, the soft-start capacitor CS1 is charged by the constant-current circuit I1, and thereby, the voltage Vs1 (the voltage of the second non-inverting input pin of the error amplifier ERA1) generated by the soft-start capacitor CS1 increases gradually from “0” (zero) V. Accordingly, at the start time of the DC-DC converter CNV, the error amplifier ERA1 generates the output signal DF1 by amplifying the voltage difference between the voltage Vs1 generated by the soft-start capacitor CS1 and the voltage Vd dividing the output voltage Vo by the resistors R1, R2. At the start time of the DC-DC converter CNV, the output voltage Vo is “0” (zero) V, and therefore, the voltage of the output signal DF1 of the error amplifier ERA1 becomes minimum, and the pulse width of the output signal QP of the PWM comparator PCMP also becomes minimum. Accordingly, the on-term of the main switching transistor T1 becomes minimum, and thereby, the inrush current is prevented.
Besides, the voltage Vs1 generated by the soft-start capacitor CS1 is a voltage defining the output voltage Vo, and increases gradually owing to the constant-current circuit I1 while talking a definite period of time. Accordingly, the output voltage Vo increases in proportion to the voltage Vs1. Consequently, a rising slope of the output voltage Vo is defined by a rising slope of the voltage Vs1. When the voltage Vs1 increases to be higher than the reference voltage Ve1, the error amplifier ERA1 generates the output signal DF1 by amplifying the voltage difference between the reference voltage Ve1 and the voltage Vd. Consequently, after the voltage Vs1 reaches the reference voltage Ve1, the output voltage Vo is defined by the reference voltage Ve1. Incidentally, at a stop time of the DC-DC converter CNV, the soft-start capacitor CS1 is discharged via the discharge resistor RD1, the voltage Vs1 generated by the soft-start capacitor CS1 decreases gradually, and therefore, it is possible to decrease the output voltage Vo gradually.
FIG. 3 shows an appearance of a rising/falling of the output voltage in the DC-DC converter in FIG. 1. When the DC-DC converter CNV is started at time t1, the soft-start capacitor CS1 is charged by the constant-current circuit I1 because the switch circuit SW1A turns on-state and the switch circuit SW1B turns off-state. As a result, the voltage Vs1 generated by the soft-start capacitor CS1 increases gradually in accordance with the passage of time. Accordingly, the output voltage Vo also increases gradually in accordance with the passage of time. When the voltage Vs1 reaches the reference voltage Ve1 at time t2, the output voltage Vo reaches the rated value (3.3 V), and after that, the output voltage Vo is kept constant controlled by the reference voltage Ve1.
When the DC-DC converter CNV is stopped at time t3, the soft-start capacitor CS1 is discharged by the discharge resistor RD1 because the switch circuit SW1A turns off-state and the switch circuit SW1B turns on-state. As a result, the voltage Vs1 generated by the soft-start capacitor CS1 decreases gradually in accordance with the passage of time. Accordingly, the output voltage Vo also decreases gradually in accordance with the passage of time. When the voltage Vs1 reaches “0” (zero) V at time t4, the output voltage Vo also reaches “0” (zero) V, and all of the circuits in the DC-DC converter CNV terminates the operations at the time when the output voltage Vo becomes “0” (zero) V.
As stated above, several methods are known preventing the inrush current of the DC-DC converter, but these methods are for a DC-DC converter of which output is controlled by a single control signal such as a constant-voltage control type DC-DC converter and a constant-current control type DC-DC converter. There exists a DC-DC converter of which output is controlled by a plurality of control signals such as a constant-voltage/constant-current control type DC-DC converter usually used as a charging circuit of a secondary battery (a lithium ion secondary battery and so on) among the DC-DC converters.
When a load is a passive load, an output current in proportion to an output voltage and in inverse proportion to a load impedance flows in the constant-voltage/constant-current control type DC-DC converter, when the DC-DC converter starts the operation and the output voltage is generated. On the other hand, when the load is an active load (for example, the secondary battery), the output current does not flow immediately even if the DC-DC converter starts the operation and the output voltage is generated. The output current is “0” (zero) A until the output voltage becomes higher than a voltage of the load, and the output current begins to flow when the output voltage becomes higher than the voltage of the load. When the constant-voltage/constant-current control type DC-DC converter is used as the charging circuit of the secondary battery, there has been a problem that an uncontrolled state exists and an inrush current is generated because it takes a long time before the control signals taking part in an output control are switched (a large-and-small relation between the voltage of the control signal for the output voltage and the voltage of the control signal for the output current is replaced).
Incidentally, as prior arts, for example, Japanese Unexamined Patent Application Publication No. Hei 9-154275, Japanese Unexamined Patent Application Publication No. Hei 10-323026, Japanese Unexamined Patent Application Publication No. 2005-354845, Japanese Unexamined Patent Application Publication No. 2005-323413, and Japanese Unexamined Patent Application Publication No. 2005-304279 can be cited.